modelsim
VCD Dump of only a sub part of the design via modelsim
I have a big design that includes a test-bench, some testing circuit and the circuit under test itself.[详细]
2023-03-27 11:47 分类：问答warning message at the prompt
I\'m tr开发者_C百科ying to simulate a testbench. I\'m not getting the waveforms also i\'m getting the following warning message at the prompt. Is it because of the=is warning that my code does not sim[详细]
2023-02-28 05:11 分类：问答ModelSim doesn't recognize the parameter data type?
Here is some Verilog code that I\'m trying to run in Modelsim. parameter Data_width = 8; //DATA SIZE input CLK, RST;[详细]
2023-02-17 23:40 分类：问答How to restart a Verilog simulation in Modelsim
I\'m trying 开发者_如何学编程to debug a Verilog module. I find it tedious to have to stop a simulation, modify code, and then go through the process of starting the simulation again. Is there an easie[详细]
2023-02-15 22:27 分类：问答Why does Modelsim 10 not compile older code?
I just recently upgraded to Modelsim 10 and when I recompiled all my code, only 30 out of 37 compiled. Those that wouldn\'t compile had a common error[详细]
2023-02-06 23:15 分类：问答Modelsim: how to setup 27 MHz clock
I want to setup a 27 MHz clock signal in ModelSim. I usually setup 开发者_如何学JAVAa clock by right clicking that signal -> clock -> setup period. For example, 50 MHz clock -> 20 ns or[详细]
2023-01-28 14:10 分类：问答modelsim source code
The following is some modelsim cod开发者_如何学JAVAe: begin tb_in_top = 0; #5 tb_in_top = 4\'b0000;#5 tb_in_top = 4\'b0001;[详细]
2023-01-15 11:49 分类：问答Global declarations are illegal in Verilog 2001 syntax!
I have wr开发者_运维知识库itten something small in verilog: `define LW 6\'b100011 `define SW 6\'b101011[详细]
2022-12-27 06:47 分类：问答
![Interactive visualization of a graph in python [closed]](https://www.devze.com/res/2023/04-10/09/92d32fe8c0d22fb96bd6f6e8b7d1f457.gif)
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