vhdl

相关标签：javascript jquery android 多少钱 iPhone

SRA can not have such operands?

I have coded an algorithm in VHDL but I have this message that I don\'t understand \"sra/sla can not have such operands in this context.\". Any help please?[详细]

2023-02-03 20:10 分类：问答
How to manage reset signal for VHDL test benches?

I have a very simple vhdl testbench that should run. My components all have a reset signal, so that registers are set to 0 and other components correctly initialized... but... if I create acommon sign[详细]

2023-02-03 06:48 分类：问答
example extending LEON SOC with custom peripheral, AMBA AHB slave

Has anyone here extended LEON3 softcore with custom hw? I\'m looking for basic example how to add custom peripheral to AMBA AH开发者_JS百科B busMay be this document can help ?[详细]

2023-02-03 01:47 分类：问答
Delta-sigma DAC from Verilog to VHDL

The code below implements a Delta-sigma DAC in Verilog, from a Xilinx application note and I want to write equivalent VHDL code. I don\'t know anything about Verilog and I\'m beginner in VHDL so I had[详细]

2023-02-01 17:58 分类：问答
Reading an image to FPGA from PC and Back

I need to read a small image (tif format) from PC to FPGA kit (ALTERA DE2-70) for processi开发者_StackOverflow社区ng, then write it back to PC. I have no idea how to do it in Verilog?[详细]

2023-01-31 09:54 分类：问答
FPGA efficient (a)synchronous resets

I remember reading a while ago that either asynchronous or synchronous resets are more efficiently implemented in FPGAs since the flip flops already have one, but the 开发者_开发技巧other would requir[详细]

2023-01-31 00:53 分类：问答
VHDL process style

I have been reading through va开发者_高级运维rious questions on here, as I am learning VHDL and always looking to improve. However, this comment made me curious:[详细]

2023-01-29 17:09 分类：问答
TAP (Test Anything Protocol) module for VHDL

Is there a TAP (Test Anything Protocol) implementation for VHDL? It would be nice because then I could use prove to check my results automatically.There are also nice formatting swuites such as smolde[详细]

2023-01-28 14:26 分类：问答
Modelsim: how to setup 27 MHz clock

I want to setup a 27 MHz clock signal in ModelSim. I usually setup 开发者_如何学JAVAa clock by right clicking that signal -> clock -> setup period. For example, 50 MHz clock -> 20 ns or[详细]

2023-01-28 14:10 分类：问答
How is a variable shown in a RTL viewer in Quartus?

How is a variable depicted in a RTL viewer in Quartus. I open RTL viewer and it does not show any register for a variable.[详细]

2023-01-28 10:49 分类：问答