vhdl

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Is my VHDL sentence allowed?

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_1164_unsigned.all; ENTITY alu IS PORT (a: IN STD_LOGIC_VECTOR (15 DOWNTO 0);[详细]

2023-02-09 10:28 分类：问答
Whats wrong with this VHDL code

I have this VHDL code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;[详细]

2023-02-08 23:21 分类：问答
VHDL: Converting from floating point to fixed point explanation?

In the Designer\'s Guide to VHDL in Chapter 6.2 there is an entity and architecture body for a converter from floating point to fixed point representation. I\'m confused by it[详细]

2023-02-08 11:16 分类：问答
What is negation (not) of a bit vector in VHDL

What does it mean to do a negation of a bit vector in VHDL? For example if I have 10100111 which is a bit vector called temp and I do something like temp := no开发者_运维知识库t temp what will my outp[详细]

2023-02-08 10:38 分类：问答
Array indexes to wide for array

I h开发者_开发知识库ave the following problem when accessing arrays in VHDL: Say I have an array which is not of size 2^n, for example of size 6.[详细]

2023-02-08 10:17 分类：问答
Conditional Assignments in a 'With Select' block

Is it possible to add conditional asignments to a signal from within a \'with select\' block.eg. with state select[详细]

2023-02-07 00:58 分类：问答
Why does Modelsim 10 not compile older code?

I just recently upgraded to Modelsim 10 and when I recompiled all my code, only 30 out of 37 compiled. Those that wouldn\'t compile had a common error[详细]

2023-02-06 23:15 分类：问答
What to use for VHDL/digital-logic simulation on Mac OS X

I suddenly realized that there is no Altera Quartus or Xilins ISE or ModelSim on Mac OS X. What do people use to at least simulate VHDL and schematic designs on M开发者_Go百科acs?Try GHDL (alternate[详细]

2023-02-06 20:08 分类：问答
Where to force xilinx ISE to use block-rams?

I synthesized a small device to test the block-ram inference. I got a message from XST : The small RAMwill be[详细]

2023-02-04 01:46 分类：问答
VHDL explanation in words

I started with VHDL course for beginners a few days ago. I’ve got a code (under) and I’m trying to understand what kind of circuit it shows and how the different steps are functioning.[详细]

2023-02-04 01:39 分类：问答

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vhdl

Is my VHDL sentence allowed?

Whats wrong with this VHDL code

VHDL: Converting from floating point to fixed point explanation?

What is negation (not) of a bit vector in VHDL

Array indexes to wide for array

Conditional Assignments in a 'With Select' block

Why does Modelsim 10 not compile older code?

What to use for VHDL/digital-logic simulation on Mac OS X

Where to force xilinx ISE to use block-rams?

VHDL explanation in words

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