vhdl

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Datatype problem in simple IF statement in VHDL

I have a really weird开发者_如何学C problem and I am not 100% why the compiler is complaining. The code is as follows:[详细]

2023-02-14 14:53 分类：问答
Why is there a delay in my VHDL combinational logic within a process?

I\'m creating a testbench for combinational logic, where a, b, cin are inputs in to an instantiated unit under test.All that ap开发者_如何学Gopears to be working fine.[详细]

2023-02-14 13:50 分类：问答
Explicitly define how LUTs and slices are used in Xilinx XST tool?

I\'m trying to implement some very specific behavior of LUTs and slices, written in VHDL for Xilinx Virtex 5 FPGA synthesized using XST tool(s).I don\'t know if I can achieve my behavior by having the[详细]

2023-02-14 11:08 分类：问答
Question regarding XST bitstream generation

I have a very simple VHDL module, consisting of a few lines of code. The thing is, when I generate the bitstream, I end[详细]

2023-02-14 09:31 分类：问答
Doxygen: Seamless documentation for project with C++ and VHDL

I\'m setting up a documentation about some sort of Library which consists of a C/C++ part and a VHDL part, plus some instructive doxygen-only pages. They have to be put into one self-contained group.[详细]

2023-02-13 07:17 分类：问答
Simulation vs hardware mismatch

I have a very simple problem but I do not get my head around what is going wrong. Essentially, the whole thing works fine when simulating it, however, having it[详细]

2023-02-10 22:17 分类：问答
What are the requirements to meet in order to ISE auto infer ram blocks?

I have this piece of IP that is supposed to be a 32 bits byte addressable memory. But I can\'t make it infer block rams, it is inferring a huge amount of flip flops...[详细]

2023-02-10 12:18 分类：问答
Python: Code for VHDL Code Generator

I am trying to make a ROM in VHDL language, I am using this template I found on http://www.edaboard.com/thread38052.html :[详细]

2023-02-10 02:20 分类：问答
VHDL: How to convert a floating point number to integer

I want to pass a from a floating point number to a integer number. Basically I have a floating point number between 1 and 0, with three decimal places 开发者_StackOverflow社区and I want to pass it to[详细]

2023-02-09 21:59 分类：问答
Does anybody have quantitative data on VHDL versus Verilog use?

VHDL and Verilog serve the same purpose, but most engineers favor one of both languages. I want to find out who favors which language.[详细]

2023-02-09 18:20 分类：问答