vhdl

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VHDL group multiple std_logic_vectors output into a single std_logic_vector

I have to design a 32-bit ALU by aggregating 8 4-bit ALU\'s I\'ve already designed. What I can\'t figure out is how to take the 8 4-bit signals and link them to the 32-bit signals for the 32-bit ALU.[详细]

2023-02-23 01:17 分类：问答
Understanding types in SystemC

I am a beginner in SystemC programming and there is one thing I noticed (look开发者_开发知识库ing in the SystemC official documentation): all types that I used to deal with in VHDL simulations have no[详细]

2023-02-22 07:57 分类：问答
Purpose to providing more than one architecture?

I\'m in the process of learning VHDL and I\'m trying just learning from examples, syntax guides, and experiments.[详细]

2023-02-21 20:45 分类：问答
Are VHDL character substitutions ever used in real life?

VHDL allows the following substitutions, presumably because some computers might not s开发者_Python百科upport the vertical bar (or pipe symbol) (|) or the hash (or pound sign / number sign) (#):[详细]

2023-02-20 03:44 分类：问答
Is there a VHDL equivalent to Verilog's @(*), i.e., automatic process sensitivity list

It is easy to update a combinatorial process and forget to update the sensitivity list. In Verilog the @(*) was introduced to say the sensit开发者_运维问答ivity list is what is used in this process. I[详细]

2023-02-18 16:33 分类：问答
How to do a VHDL "typedef"

I want to \"create\" a type \"my_type\", which is a开发者_如何学Python std_logic_vector(...), like this C/VHDL fake code:[详细]

2023-02-17 07:31 分类：问答
Simple VHDL 4 to 1 MUX testbench is hanging

-----------begin part1.vhdl--------------------- library ieee; use ieee.std_logic_1164.all; entity part1 is[详细]

2023-02-16 16:38 分类：问答
Tool to find commented out VHDL code

This question asks the general question. I\'m asking about VHDL in particular, since the tools 开发者_运维知识库that question\'s answer mentions are for Java and PL/SQL. It doesn\'t need to be perfect[详细]

2023-02-15 09:02 分类：问答
VHDL: Finding out/reporting bit width/length of integer (vs. std_logic_vector)?

Say I need a signal to represent numbers from 0 to 5; obviously this needs 3 bits of std_logic to be represented (i.e if MAXVAL=5, then bitwidth= {wcalc \"floor(logtwo($MAXVAL))+1\"}).[详细]

2023-02-15 00:31 分类：问答
What's wrong with my VHDL testbench?

I\'ve created a testbench 开发者_高级运维to test an adder carry circuit (although it doesn\'t matter what the circuit is doing)[详细]

2023-02-14 17:40 分类：问答