vhdl

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Can anybody let me know what is the problem with the following vhdl code?

I am getting error as \"ERROR:Xst:827 - \"C:/1553/decoder_copy/decoder.vhd\" line 265: Signal no_words cannot be synthesized, bad synchronous description\".[详细]

2023-03-06 13:49 分类：问答
How to convert 24MHz and 12MHz clock to 8MHz clock using VHDL?

I am writing a开发者_运维知识库 code using VHDL to convert 24MHz and 12 MHz clock to 8 MHz clock. Can anyone please help me in this coding? Thanks in advance. Is this for an FPGA? Or something else? A[详细]

2023-03-06 02:57 分类：问答
Implementing a FSM in VHDL

Just wondering if I\'m implementing a finite state machine in VHDL whether or not I need to state what all of the outputs are in every possible state? Even if I know that some outputs won\'t change fr[详细]

2023-03-06 02:18 分类：问答
VHDL TG68 core data_in and data_out to datainout

I want to use tg68 core but there is a problem. When I compile my design in Altera Quartus it gives me 16 data_in and 16 data_out signals, and i need to join them into inout pins.[详细]

2023-03-05 21:23 分类：问答
Can't infer register for ... at ... because it does not hold its value outside the clock edge

This must be the most common problem among people new to VHDL, but I don\'t see what I\'m doing wrong here! This seems to conform to all of the idioms that I\'ve seen on proper state machine design. I[详细]

2023-03-05 08:16 分类：问答
Single Port RAM in VHDL?

I want a RAM in VHDL (that can synth开发者_开发问答esize on Xilinx, Altera..) with the following \'catch\' -[详细]

2023-03-03 03:25 分类：问答
What are best practices for optimizing pipeline throughput for fpga implementations?

How does one for example make the best use of retiming and/or c-slow to make the most of a given pipeline.[详细]

2023-03-01 00:27 分类：问答
Unsigned logic, vector and addition - How?

I\'m creating a program counter that is supposed to use only unsigned numbers. I have 2 STD_LOGIC_VECTOR and a couple of STD_LOGIC. Is there anything I need to do so that they only use unsigned? At[详细]

2023-02-26 08:30 分类：问答
create two elements connecting to one mux 41 and 21

I have big problem because i dont uderstand properly how make my homework. Well i have to make something like this:[详细]

2023-02-25 22:28 分类：问答
How to assign pins in Quartus II

We are looking at moving some code into a CPLD or FPGA in order to make it faster. I have worked with Xilinks and their suite of tools before, but for some reason it was decided that we\'d use Altera[详细]

2023-02-24 07:15 分类：问答