vhdl

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VHDL: Is it possible to define a generic type with records?

I am trying to define a complex type (i.e, a type that consists of both a real and imaginary part) and am trying to find out a way to make it generic.[详细]

2023-03-12 22:45 分类：问答
Creating a frequency divider in VHDL

MAJOR EDIT: Problem was solved after reading Will Dean\'s comment. The original question is below the revised code:[详细]

2023-03-11 03:04 分类：问答
Generate State Machine graph from VHDL code?

Is t开发者_JAVA百科here any quite good tool to generate State Machine graph from VHDL code? I\'m using Xilinx ISE Webpack. Cheers!Active HDL has a feature called \"Code2Graphics\" which supports this.[详细]

2023-03-10 16:50 分类：问答
How to reduce number of logic elements

I am trying to reduce the number of logic elements in my vhdl code. I am using quartus II to program a Altera DE2 FPGA开发者_如何学JAVA. Can someone please give some advice on how I can do that ?[详细]

2023-03-10 05:50 分类：问答
My counter "4-digit BCD Counter" does not work well!

I have designed 4-digit BCD Counter and BCD-to-7segment Converter as a project of one of my courses in the university.[详细]

2023-03-10 00:14 分类：问答
what's wrong with my VHDL sine function gen?

library IEEE; use IEEE.MATH_REAL.ALL; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.NUMERIC_STD.ALL;[详细]

2023-03-09 18:12 分类：问答
Where to declare a constant or type used in an entity declaration?

If I haven\'t misunderstood this completely, a constant or type can not be declared at the top level of a file. Only packages, entities, architectures et.c. can be declared there. They can be declared[详细]

2023-03-09 04:31 分类：问答
"Warning C0007 : Architecture has unbound instances" issue!

I have the following source code from the CD attached with \"Fundamental of Digital Design\" book. When I tried run the program, it gave me the following error:[详细]

2023-03-08 23:12 分类：问答
Implementing A Digital Clock in VHDL

I am trying to make a digital clock using VHDL and I want to display the result on the VGA screen. But I am stuck with the idea that how can I convert the integer type into BCD? Because right now I am[详细]

2023-03-08 07:21 分类：问答
How to use generic parameters that depend on other generic parameters for entities?

I am trying to convert some Verilog code that produces a slower clock from a faster clock for a UART module.The original verilog code is based on the module over at fpga4fun.com, and this is my attemp[详细]

2023-03-07 18:24 分类：问答