vhdl

相关标签：javascript jquery android 多少钱 iPhone

using variable before it is defined

process is variable a_var, b_var : std_logic ? begin wait until ( rising_edge ( clk ) ); a_var := x开发者_开发问答 or y ;[详细]

2023-03-27 22:36 分类：问答
VCD Dump of only a sub part of the design via modelsim

I have a big design that includes a test-bench, some testing circuit and the circuit under test itself.[详细]

2023-03-27 11:47 分类：问答
how can one compile .vhd under ghdl?

My first question :I wonder how you compile your vhdl file under ghdl ? In c/c++, we use -Werror -Wunused-variable[详细]

2023-03-26 09:00 分类：问答
Is initialization necessary?

In VHDL, is initialization necessary when creating a signal or a vector? What happens if one forgets to initializ开发者_Go百科e a signal or integer value?In simulation, if you do not set an initial v[详细]

2023-03-25 13:38 分类：问答
necessity of 'event

I have used below statement, frequently. However, I wonder if ( clock\'event and clock = \'1\' ) then[详细]

2023-03-23 21:40 分类：问答
Xilinx ISE fails to use std_logic_1164

I have Xilinx ISE 13.1 installed on an ACER laptop with Win7 (64bit). After installing the software (WebPACK version) I created an empty VHDL module and ran \"check syntax\". The process failed with[详细]

2023-03-23 08:57 分类：问答
Sharing (including?) generics in VHDL between files?

Assume I have this simple core with generics as genertest.vhd: --------------------------------------------------------------------------[详细]

2023-03-20 16:41 分类：问答
How to stream a small video in spartan 3e fpga?

By Using cosmiac tutorial 13 http://www.cosmiac.org/tutorial_13.html and ISE 10.1 the pdf file shows how to generate an image and you can download the project by clicking the first .zip file. At the e[详细]

2023-03-19 21:00 分类：问答
how to define an input in Entity with 2D-array?

i want to define an input with 2D array in an entity how can i make th开发者_Go百科at i tried to define a d input by this code[详细]

2023-03-15 00:38 分类：问答
Is there a reason to initialize (not reset) signals in VHDL and Verilog?

I have never initialized signals. That way any signal missing a reset or assignment would be unknown or initialized. In some reference code they have initialization. 开发者_运维技巧This defeats what I[详细]

2023-03-13 10:52 分类：问答