vhdl
State to std_logic
I have defined my state as follows: type state_type is (s0, s1, s2, s3); signal state: state_type; Now I would like to use this state information to form another signal[详细]
2023-01-20 06:57 分类:问答Simple State Machine Problem
I have a very simple FSM which should drive some output signals of an external RAM. The problem that I have comes with handling the data bus[详细]
2023-01-20 00:30 分类:问答Wrapping and switching between similar entities in VHDL
I want to describe an entity that can either function normally or be put i开发者_StackOverflown a test mode. The general design I have is a top level entity that wraps the \"real\" entity and a test e[详细]
2023-01-16 07:07 分类:问答VHDL Case/When: multiple cases, single clause
Inside a process I have something like this: CASE res IS WHEN \"00\" => Y <= A; WHEN \"01\" => Y <= A;[详细]
2023-01-15 21:22 分类:问答Why do I need to redeclare VHDL components before instantiating them in other architectures?
I\'ve been scratching my head since my first VHDL class and decided to post my question here. Given that 开发者_如何学运维I have a declared entity (and also an architecture of it) and want to instant[详细]
2023-01-15 07:17 分类:问答Creating a VHDL backend for LLVM?
LLVM is very modular and allows you to fairly easily define new backends.However most of the documentation/tutorials on creating an LLVM backend focus on adding a new processor instruction set and reg[详细]
2023-01-15 00:43 分类:问答Redundant loop inside a process (VHDL)?
I\'m taking a university course to learn digital design using VHDL, and was doing some reading in the book the other day where I came across the following piece of code:[详细]
2023-01-14 19:21 分类:问答how much for Sound (ADC) reading in 24khz?
how much \"sound inputs\" of high fidelify (128K 44kH) may be made via ordinary FPGA (Xilinx Spartan 3, what-so-ever) without using external开发者_JAVA百科 ADC converters (only voltage-balanced input[详细]
2023-01-14 19:10 分类:问答What is ModelSim output file and how to load hex file on a ROM?
I want to simulate a microprocessor designed using VHDL in ModelSim. I wanted to know what the output file format of the simulation is?[详细]
2023-01-14 12:36 分类:问答Simulation not working - port mapping wrong?
VHDL code First of all, sorry for the redirect, but it\'s easier that way. I\'m building a digital clock, but as you can see, clock_AN and clock_seg_out do not change. Is this caused b开发者_开发知识[详细]
2023-01-14 08:55 分类:问答