fpga

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Looking for library declaration of IP Module

I want to use the Xilinx hardware module of the ICAP controller in my own design. This module uses the following library:[详细]

2023-01-21 16:17 分类：问答
Reset an Altera M9K's content to 0 (power-up value)

Good day, I am working on a Stratix III FPGA which contains M9K block memories, the contents of which are conveniently initialised to zero on power-on. This suits my application very well.[详细]

2023-01-21 11:29 分类：问答
State to std_logic

I have defined my state as follows: type state_type is (s0, s1, s2, s3); signal state: state_type; Now I would like to use this state information to form another signal[详细]

2023-01-20 06:57 分类：问答
Simple State Machine Problem

I have a very simple FSM which should drive some output signals of an external RAM. The problem that I have comes with handling the data bus[详细]

2023-01-20 00:30 分类：问答
how much for Sound (ADC) reading in 24khz?

how much \"sound inputs\" of high fidelify (128K 44kH) may be made via ordinary FPGA (Xilinx Spartan 3, what-so-ever) without using external开发者_JAVA百科 ADC converters (only voltage-balanced input[详细]

2023-01-14 19:10 分类：问答
Sending UDP packets via Java

I\'m trying to se开发者_StackOverflow社区nd UDP packets from my PC to an FPGA via my laptop\'s ethernet cable. I\'ve been using Java\'s DatagramPacket and DatagramSocket to send the UDP packets. Howev[详细]

2023-01-12 00:39 分类：问答
Starting FPGA Programming [closed]

Closed. This question needs to be more focused. It is not currently accepting answers. Want to improve开发者_JAVA百科 this question? Update the question so it focuses on one problem only b[详细]

2023-01-10 17:54 分类：问答
Import Code from FPGA Board (Spartan 3E)

Is there any way to import code from an already programmed FPGA board, in this case, it is a Spartan 3E board. That is to say, verilog code has already been uploaded to it, so I would like a way to re[详细]

2023-01-08 19:47 分类：问答
Signals and Variables in VHDL (order) - Problem

I have a signal and this signal is a bitvector (Z). The length of the bitvector depends on an input n, it is not fixed. In order to find the length, I have to do some computations. Can I define a sign[详细]

2023-01-02 05:56 分类：问答
Configuration Management for FPGA Designs

Which configuration management tool is the best for FPGA designs, specifically Xilinx F开发者_运维技巧PGA\'s programmed with VHDL and C for the embedded (microblaze) software?There isn\'t a \"best\",[详细]

2023-01-02 03:32 分类：问答