fpga
example extending LEON SOC with custom peripheral, AMBA AHB slave
Has anyone here extended LEON3 softcore with custom hw? I\'m looking for basic example how to add custom peripheral to AMBA AH开发者_JS百科B busMay be this document can help ?[详细]
2023-02-03 01:47 分类:问答Reading an image to FPGA from PC and Back
I need to read a small image (tif format) from PC to FPGA kit (ALTERA DE2-70) for processi开发者_StackOverflow社区ng, then write it back to PC. I have no idea how to do it in Verilog?[详细]
2023-01-31 09:54 分类:问答How are FPGAs "Updated"
I seem to be under the impression that FPGAs can be updated while the chip is running; and I need to know开发者_StackOverflow if that is correct or not.[详细]
2023-01-30 01:46 分类:问答FPGA measure accurate times
We are checking how fast is an a开发者_如何学JAVAlgorithm running at the FPGA vs Normal Quad x86 computer.[详细]
2023-01-27 16:24 分类:问答Universal shift arithmetic right in VHDL
I am designing universal shift arithmetic operator. Is there a better way to achieve it besides using the 32bit multiplexer (decoder) in a way presented bellow?[详细]
2023-01-25 12:50 分类:问答Preserving the widths of ports
I am trying to re-use netlists in other designs without the success. I have a component which is translated to the netlist:[详细]
2023-01-25 07:06 分类:问答Losing link to the FPGA device
I am trying to debug somewhat strange problem in the device driver for the PCIe FPGA device. Both the device driver and the FPGA image are developed in the house.[详细]
2023-01-25 02:53 分类:问答Problem with net instantiation
I have a very simple statemachine that sets some control signals to interact with a third party IP. The code looks roughly as follows:[详细]
2023-01-23 04:39 分类:问答How do I implement a synthesizable DPLL in Verilog?
I开发者_Go百科s there any straight forward way to implement an all digital phase lock in synthesizable Verilog? Everything (including the VCO) should be synthesized. The signals I\'m looking to lock t[详细]
2023-01-22 16:09 分类:问答Error adding std_logic_vectors
I w开发者_运维技巧anna have a simple module that adds two std_logic_vectors. However, when using the code[详细]
2023-01-22 14:30 分类:问答