fpga

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C-to-hardware compiler (HLL synthesis) [closed]

Closed. This question needs to be more focused. It is not currently accepting answers. Want to improve this question? Update the question so it focuses on one problem only by editing this[详细]

2023-02-22 23:36 分类：问答
What is redundant versus non-redundant number format?

I\'m having trou开发者_如何学编程ble understanding the algorithm being used in this FPGA circuit.It deals with redundant versus non-redundant number format.I have seen some mathematical (formal) defin[详细]

2023-02-22 03:05 分类：问答
Unable to Implement Simple ALU

I have a basic 8-bit ALU described in Verilog. I am trying to implement the design, but I am getting error messages:[详细]

2023-02-17 19:08 分类：问答
Explicitly define how LUTs and slices are used in Xilinx XST tool?

I\'m trying to implement some very specific behavior of LUTs and slices, written in VHDL for Xilinx Virtex 5 FPGA synthesized using XST tool(s).I don\'t know if I can achieve my behavior by having the[详细]

2023-02-14 11:08 分类：问答
Is it possible to program Microblaze without EDK, on any Xilinx FPGA?

Is it possible to program开发者_运维知识库 Microblaze without EDK, on any Xilinx FPGA device ?[详细]

2023-02-13 04:11 分类：问答
Driving bidirectional lines in Verilog

this question probably wont be explained very well and that\'s because I don\'t really understand what\'s happening in my design.[详细]

2023-02-12 20:48 分类：问答
Automated tracing use of variables within source code

I\'m working with a set of speech processing routines (written in C) meant to be compiled with the mex command on MATLAB. There is this C-function which I\'m interested in accelerating using FPGA.[详细]

2023-02-11 05:30 分类：问答
what is a differential i/o

In the world of the Spartan 3E Fpga the documentatio开发者_JAVA百科n says Most pins can be paired together to form differential I/Os.[详细]

2023-02-10 22:56 分类：问答
computer on PCIe card

Does anyone know a COM which is put on a PCIe card, which has some flash memory, some RAM, JTAG support (or some kind of debugging support), some input ports like USB, perhaps support some output like[详细]

2023-02-05 04:17 分类：问答
Where to force xilinx ISE to use block-rams?

I synthesized a small device to test the block-ram inference. I got a message from XST : The small RAMwill be[详细]

2023-02-04 01:46 分类：问答