fpga

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Using Slice Block in Simulink

I 开发者_如何学运维am having some trouble using the Slice block(Xilinx Bit Slice Extractor).[详细]

2023-03-06 10:26 分类：问答
How to convert 24MHz and 12MHz clock to 8MHz clock using VHDL?

I am writing a开发者_运维知识库 code using VHDL to convert 24MHz and 12 MHz clock to 8 MHz clock. Can anyone please help me in this coding? Thanks in advance. Is this for an FPGA? Or something else? A[详细]

2023-03-06 02:57 分类：问答
Timing Signal understanding in Xilinx Simulink

I am having some trouble understanding the concept of Timing Signals in Simulink (Xilink Library). I will explain with an example,[详细]

2023-03-05 15:36 分类：问答
Can't infer register for ... at ... because it does not hold its value outside the clock edge

This must be the most common problem among people new to VHDL, but I don\'t see what I\'m doing wrong here! This seems to conform to all of the idioms that I\'ve seen on proper state machine design. I[详细]

2023-03-05 08:16 分类：问答
How to obtain a absolute of a number in Xilinx Simulink?

I need to get the absolute of the signal in Xilinx Simulink. 开发者_如何学编程I can use a mcode block and write matlab code to achieve it. But, just curious if there is a better way of doing it.[详细]

2023-03-04 13:08 分类：问答
Critical Path from FPGA in Mentor

I am working with Mentor FPGA doing RTL design with moduleware and vhdl.Right now I am looking at th开发者_如何转开发e Mentor Graphics Precision RTL synthesis GUI.Does anyone know how I can get a crit[详细]

2023-03-04 00:04 分类：问答
Sine of the signal in Xilinx Simulink

I am implementing a DQPSK modulator and Demodulator. I would like to calculate the exp(1j*Phase) in Simulink.[详细]

2023-03-03 14:50 分类：问答
DBPSK Demodulation in Simulink using Xilinx blockset

I am trying to build a DBPSK demodulator using Simulink and Xilinx blockset. I calculate the Phase Difference of the Successive samples like this :[详细]

2023-03-02 19:08 分类：问答
What are best practices for optimizing pipeline throughput for fpga implementations?

How does one for example make the best use of retiming and/or c-slow to make the most of a given pipeline.[详细]

2023-03-01 00:27 分类：问答
Design Flow to create a bootable SPI Flash (PROM File) for a Xilinx Spartan-6 containing Configuration bitsream AND Microblaze software

I would like to know the proper procedure to cr开发者_C百科eate a PROM file (.MCS) for a serial SPI Flash that include BOTH the FPGA configuration bitstream and the software to be used by the Microbla[详细]

2023-02-25 21:26 分类：问答