verilog

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Reading an image to FPGA from PC and Back

I need to read a small image (tif format) from PC to FPGA kit (ALTERA DE2-70) for processi开发者_StackOverflow社区ng, then write it back to PC. I have no idea how to do it in Verilog?[详细]

2023-01-31 09:54 分类：问答
Is $readmem synthesizable in Verilog?

I am 开发者_StackOverflow社区trying to implement a microcontroller on an FPGA, and I need to give it a ROM for its program. If I use $readmemb, will that be correctly synthesized to a ROM? If not, wha[详细]

2023-01-28 06:14 分类：问答
64 bit double precision floating point CPU using verilog

how to conve开发者_Go百科rt 64 bit decimal value into the 64 bit binary value?? what is the range of the decimal values of 64 bit????[详细]

2023-01-26 10:04 分类：问答
DWT in Verilog(FPGA Implementation)

Can anyone tell me how to write a verilog code for DWT of an image and download in to fpga. Actually my project is to write a verilog code to perform discrete wavelet transform of a medical image, ca[详细]

2023-01-26 09:44 分类：问答
Verilog to GDSII compiler (open-source)

May be this question a bit not for StackOverflow, but both compilers and Verilog (which can be considere开发者_StackOverflowd as programming language) are related to this project.[详细]

2023-01-25 06:17 分类：问答
How to sign-extend a number in Verilog

I\'m working on a simple sign-extender in Verilog for a processor I\'m creating for Computer Architecture.[详细]

2023-01-24 19:22 分类：问答
How do I implement a synthesizable DPLL in Verilog?

I开发者_Go百科s there any straight forward way to implement an all digital phase lock in synthesizable Verilog? Everything (including the VCO) should be synthesized. The signals I\'m looking to lock t[详细]

2023-01-22 16:09 分类：问答
Can't make sense of error in System Verilog

I tried to compile code module counter( input clk, input upSignal, input downSignal, output [7:0] count ); always_ff @(posedge clk) begin[详细]

2023-01-21 17:24 分类：问答
Reset an Altera M9K's content to 0 (power-up value)

Good day, I am working on a Stratix III FPGA which contains M9K block memories, the contents of which are conveniently initialised to zero on power-on. This suits my application very well.[详细]

2023-01-21 11:29 分类：问答
modelsim source code

The following is some modelsim cod开发者_如何学JAVAe: begin tb_in_top = 0; #5 tb_in_top = 4\'b0000;#5 tb_in_top = 4\'b0001;[详细]

2023-01-15 11:49 分类：问答