verilog

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When and why do you have to use DUT when testing a verilog module?

I just started learning about software test benches for verilog modules. I noticed that when the test bench calls the module, it puts DUT i开发者_开发百科n between the module name and the sensitivity[详细]

2023-02-15 12:27 分类：问答
CRC-16 Computation in IEEE 802.11b

I would like to understand the CRC compuation in the Header field of IEEE 802.11b PHY. I read in the literature, CRC-16 is used and the 1\'s compliment of the reminder of the (e SIGNAL, SERVICE, and L[详细]

2023-02-13 22:22 分类：问答
Verilog doesn't have something like main()?

I understand that modules are essentially like c++ functions. Ho开发者_运维技巧wever, I didn\'t find something like a main() section that calls those functions. How does it work without a main() secti[详细]

2023-02-13 21:53 分类：问答
Driving bidirectional lines in Verilog

this question probably wont be explained very well and that\'s because I don\'t really understand what\'s happening in my design.[详细]

2023-02-12 20:48 分类：问答
Adding two single BCD digits with Verilog

Cou开发者_如何学Pythonld you please help me finding a Verilog code to add two BCD digits where the output should be BCD as well?Why not write the code yourself? It\'s not too difficult, especially if[详细]

2023-02-12 14:33 分类：问答
Does anybody have quantitative data on VHDL versus Verilog use?

VHDL and Verilog serve the same purpose, but most engineers favor one of both languages. I want to find out who favors which language.[详细]

2023-02-09 18:20 分类：问答
Looking for verilog 2001 module declaration grammar

I can find several v2k full grammars with google -- but either I am losing my mind or they are all broken in the same way with 开发者_Go百科regard to port declarations.[详细]

2023-02-09 02:39 分类：问答
Have the errors in "HDL Chip Design" by Douglas Smith ever been corrected?

My copy of \"HDL Chip Design\" by Douglas Smith is the 开发者_JAVA百科ninth printing, July 2001.[详细]

2023-02-08 16:35 分类：问答
Verilog array syntax

I\'m new to Verilog, and am having a lot of trouble with it. For example, I want to have an array with eight cells, each o开发者_运维知识库f which is 8 bits wide. The following doesn\'t work:[详细]

2023-02-08 02:38 分类：问答
Delta-sigma DAC from Verilog to VHDL

The code below implements a Delta-sigma DAC in Verilog, from a Xilinx application note and I want to write equivalent VHDL code. I don\'t know anything about Verilog and I\'m beginner in VHDL so I had[详细]

2023-02-01 17:58 分类：问答