Does anybody have quantitative data on VHDL versus Verilog use?

VHDL and Verilog serve the same purpose, but most engineers favor one of both languages. I want to find out who favors which language.

There are dozens of myths and common wisdoms about the separation between Verilog and VHDL. (ASIC / FPGA, Europe / USA, Commercial / Defense, etc.) If you ask around, people will tell you the same thing over an开发者_StackOverflow社区d over, but I want to find out if these myths are based on reality.

So my question: can anybody provide sources of quantitative data that indicate who uses VHDL and who uses Verilog? Again, I’m looking for numbers, not for gut feelings and general indications.

---

VHDL and Verilog are both fairly new and fairly specialized languages. Those two characteristics make their qualitative data hard to come by. On the other hand, we can use these characteristics to our advantage. We can attempt to infer the popularity of these languages based on the number of references that are available.

Amazon.com Book Listings By Subject

VHDL        315
Verilog     132

Google Trends: Verilog (red) vs VHDL (blue) - Source

By these numbers (and only these numbers) VHDL seems to be more widely-used than Verilog; however, there is no indication on the market share details of each.

---

I work for a large publicly traded hardware design company headquartered in Silicon Valley. We used to use VHDL, but switched to verilog in 2002(ish).

Around 2008, we switched to system verilog. As I understand it, most non-military/non-gov't contracting companies use system verilog while military/gov't contracting entities use VHDL these days.. but don't quote me...

Is this what you're asking for? If so, +1 for system verilog :)

---

I've been an ASIC and FPGA designer/verification engineer for 17 years, and I've worked on both VHDL and verilog projects. I've been at some huge name companies that use VHDL (Intel, Qualcomm, Lockheed, Raytheon). However, all the IP I've ever seen is in verilog, for whatever that's worth. Also, from my limited sample of job interviews and experience, its been pretty evenly divided between VHDL and Verilog over most of my career.

My take on it is that VHDL and Verilog were pretty even until the mid-2000's, when Verilog evolved into System Verilog, and VHDL stayed fairly static, except for minor changes. It used to be that VHDL had more non-synthesizable language features that aided verification that old-school verilog. With System Verilog, VHDL got leap-frogged in that area of strength, and never responded with an evolution of its own, so I'm (anecdotally) seeing a migration towards SV and away from VHDL.

---

At Texas Instruments, Verilog was more popular. My experience is that designers can use whichever they prefer, usually, and most agree that Verilog is easier to use and the code is shorter (fact) than equivalent VHDL. Just check any text book that has both, and you can see that difference in length of code.

---

I don't have the numbers nor any gut feelings for that matter. I'll give you some facts regarding VHDL.

[1] SystemVerilog enhances Verilog-HDL up to par with existing capabilities of VHDL (STD. 1076-2002).

[2] VHDL 2008 (STD. 1076-2008): Has anyone used the latest standard. Kindly use it and then compare with Verilog (STD. 1364-2005).

[3] SystemVerilog extends Verilog-HDL by adding a rich, user-defined type system, and adds strong-typing capabilities, especially in the area of user-defined types. ... HOWEVER the strength of type-checking in VHDL still exceeds that in SystemVerilog. ... The downside of Strong-typing is on performance; i.e. Compilation and Simulation (only when run-time checks are enabled) are slow. Slow compilation is not an issue when considering the amount of investment in the project (the reasoning at our firm).

I consider VHDL as a 'safe' language and Verilog as a 'fast' language that lets you write models quickly. The company where I work prefers safety over speed; so we use VHDL predominantly in our design flows.

Also do check out the new OS-VVM (Open Source VHDL Verification Methodology) developments.