Looking for verilog 2001 module declaration grammar

I can find several v2k full grammars with google -- but either I am losing my mind or they are all broken in the same way with 开发者_Go百科regard to port declarations. Example input:

module foo ( 
    input x, 
     output [2:0] y);
endmodule;

I can't find a grammar which will parse that syntax, but they will accept things like this as a 'port' in the list_of_port:

         { name[3:0], name2[2:0]} 
.. or ..   .name( othername )

I.e. things I expect to see in the grammar for a module instantiation port binding are supplied for a module port declaration.

Examples

http://www.externsoft.ch/download/verilog.html#module_declaration

http://www.syncad.com/VeriLogger_bnf_Syntax_Verilog_2001.htm#list_of_ports

I guess I can look into the icarus source, or Perl::Verilog. I'm hoping to get a confirmation that the grammars above are broken, though -- or can someone point out what I'm missing if not. A source for a correct grammar would be great...

---

Your first code block uses the list_of_port_declarations syntax which is valid in IEEE 1364-2001(Sec 12.3.3) and all later versions. The grammar from the first link is incomplete, the second link looks like it includes this construct

Your second code block is definitely valid. The syntax that looks like instance ports in a module definition are explicit port constructs. Not used very often, these are used when you want to present a different signal interface externally than what is used internally. Here are a few examples:

module mod1(portA);
input portA; //Implicit port named portA connected to implicit wire portA
endmodule

Here, portA is implicit and inherits the attributes from the input declaration because it shares the same identifier portA.

module mod2(.expA(sigA));
wire sigA;
endmodule

module top;
wire sigB;
mod2 modInst(.expA(sigB));
endmodule

In this example we use an explicit port for the mod2 module. Internally expA is connected to sigA but as you see in the instance modInst, we use the external name for named connections.

module mod3 (.expA({sigC,sigD}), sigF, .expB(sigG[1],sigB[3:0]));
output reg [3:0] sigC, sigD;
input wire [1:0] sigG;
input wire [7:0] sigB;
output wire sigF;
endmodule

This is also valid. Port expA assumes the width of the sigC and sigD concatenation. Same with port expB.