VHDL: Converting from floating point to fixed point explanation?

In the Designer's Guide to VHDL in Chapter 6.2 there is an entity and architecture body for a converter from floating point to fixed point representation. I'm confused by it

library ieee; use ieee.std_logic_1164 all;
entity to_fp is
   port(vec: in std_u_logic_vector(15 downto 0);
        r: out real);
end entity to_fp;

architecture behavioral of to_fp is
begin 
    behavior : process (vec) is
       variable temp: bit_vector(vec'range);
       variable negative: boolean;
       variable in开发者_开发技巧t_result: integer;
    begin
       temp := to_bitvector(vec);
       negative := temp(temp'left) = '1';
       if negative then
          temp := not temp;
       end if;
       int_result := 0;
       for index in vec'range loop
           int_result := int_result*2 + bit'pos(temp(index));
       end loop;
       if negative then
          int_result := (-int_result) -1;
       end if;
       r <= real(int_result) / 2.0**15;
    end process behavior;
end architecture behavioral;

I understand most of it. I just don't understand the for loop. How does this give us the integer representation of the bit vector? Please explain in as much detail as possible, Thanks :) .

---

for index in vec'range loop

This loops over the range of vec. In this case this (15 downto 0).

bit'pos(temp(index));

bit is an enumaration type (type BIT is ('0', '1'); in std.standard). The pos attribute returns the position number (as an integer type) of the given value. So bit'pos(...) converts a bit to an integer.

So what the loop does is convert a bit_vector to an integer.

I recommend using to_integer(unsigned(vec)) for this purpose, though. Remember to use ieee.numeric_std.all;.

The last line converts (casts) the integer to a real.