Array indexes to wide for array

I h开发者_开发知识库ave the following problem when accessing arrays in VHDL:

Say I have an array which is not of size 2^n, for example of size 6. Then, if I want to access this array using an index of width 3 bits (=ceil(log2(6))), it is clear that this index can reach two positions, 7 and 8, which are beyond the size of the array I am accessing. Xilinx ISE gives me a warning in this case.

How should I go about this? My possible solutions are as follows:

1.) Ignore the warnings. Hope synthesis is smart.

2.) Only use arrays of size 2^n. Hope unused portions of array will be optimized away.

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I suggest to ignore the warnings in this case. Synthesis can handle this.

Synthesis can also easily optimize away anything not used, but artificially increasing array sizes seems like overkill.