Conditional Assignments in a 'With Select' block

Is it possible to add conditional asignments to a signal from within a 'with select' block. eg.

with state select
    Data <= x"00" when IDLE开发者_如何转开发,
            (x"01" when Count = 0 else x"10") when DATA,
            x"FF" when others;

This doesn't compile, but is it possible to include a second variable within this block?

---

Short answer is no.

You could do something like this instead.

  process (Count, state)
    variable countData : std_logic_vector (7 downto 0);
  begin
    if Count = 0 then
      countData := x"01";
    else
      countData := x"10";
    end if;
    case state is
      when IDLE   => Data <= x"00";
      when DATA   => Data <= countData;
      when others => Data <= x"FF";
    end case;
  end process;