Whats wrong with my makefile

#####################################################################
# This is the filesystem makefile "make_BuddyAlloc".
# Author:Michael Gomes
# Date:2 jan 2011
######################################################################

#variable defination
CC = gcc
CFLAGS = -g -O2
SRC_DIR=src
INC_DIR=inc
OBJ_DIR=obj

#List of source files 
SOURCE= buddyMain.c \
  Copy.c \


#List of object files 
OBJECTS=$(addprefix $(OBJ_DIR)/,$(SOURCE:.c=.o))

#BuddyAlloc is dependent on "obj/*.o".
Budd开发者_如何学CyAlloc : $(OBJECTS)
 $(CC) $(CFLAGS) -o BuddyAlloc $<

#obj/*.o depends on src/*.c and inc/*.h, we are redirecting the object files to obj folder
$(OBJECTS):$(SRC_DIR)/$(SOURCE)  
 $(CC) $(CFLAGS) -I$(INC_DIR) -o $(OBJ_DIR)/$(OBJECTS) -c $<


#Cleans all the *.exe files
clean:
 rm -f *.exe

I have kept the source files under src folder includes under inc folder and the object files are being saved in obj folder .given above is the makefile i am trying to create for my mini project. I keep getting the error no rule to make target 'Copy.c' needed by 'obj/buddyAlloc.o', but it works fine it i dont include Copy.c, what did i do wrong?

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This line is your problem: $(OBJECTS):$(SRC_DIR)/$(SOURCE). The resulting string for the dependency (the right side of the colon) is src/buddyMain.c Copy.c. In other words, you are trying to prepend the source directory but it's only getting prepended to the first file.

There are numerous ways to fix this:

1. The manual approach:

   SOURCE = $(SRC_DIR)/buddyMain.c $(SRC_DIR)/Copy.c

2. VPATH, which adds directories to every search path (see http://www.gnu.org/software/make/manual/make.html#General-Search)

   VPATH = src

3. Or, as used in the Makefile already, use addprefix to introduce a new variable built from SOURCE:

   SRCS = $(addprefix $(SRC_DIR)/,$(SOURCE))

---

You're using GNUisms in your Makefile anyway, so why not just use a pattern rule?

$(OBJ_DIR)/%.o: $(SRC_DIR)/%.c
    $(CC) $(CFLAGS) -I$(INC_DIR) -c -o $@ $<