FPGA efficient (a)synchronous resets

I remember reading a while ago that either asynchronous or synchronous resets are more efficiently implemented in FPGAs since the flip flops already have one, but the 开发者_开发技巧other would require additional logic.

Does anyone know which way round this is? Is this the same for Xilinx, Altera, Other..

When learning, I used to add an asynchronous clear and a synchronous reset to every FSM, just in case. Is there any benefit at all to this?

Thanks for any feedback!

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To directly answer the question - most FPGAs can do either sync or async resets in their flipflops these days. In terms of adding an async clear and sync rest, I'm not sure what you acheieved by this - add the signals which are required for the function of your design (possibly including no reset at all for some flops...)

Some further advice... If you use an asynchronous reset, be very careful when you deassert it. If there's much skew on this "slow" net across your device, you may find some flops coming our of reset on a different clock cycle to others. Chaos ensues!

To avoid this, I favour creating a toplevel block which takes in your external (and presumably very asynchronous) reset signal, synchronises it to the clock and feeds it as a synchronous reset to all the flops you want resetting (in that clock domain - you may need more than one). Then the timing analyser will tell you if the skew is too much the device, and you'll ensure everything comes out of reset at once.

Xilinx have a whitepaper on this subject, but it applies equally to other FPGAs also.

For some applications you may need an asynchronously asserted reset on the IOs to ensure that certain external devices work the way you need - but still deassert it synchronously.

(PS. as you mention FPGAs, if you're not aware, there's a stackexchange proposal related to programmable logic which you may find of interest http://area51.stackexchange.com/proposals/20632/)

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Well, your best bet is to consult your specific FPGA vendor's documentation and white papers. In most of the professional design teams I've worked on, we used asynchronous resets to maintain maximum control. The choice between synchronous and asynchronous resets really depends on your design and application, however.

By the way, you might find this paper on the topic of resets from Sunburst Design interesting. Though it primarily addresses ASIC design and Verilog, it is a useful paper for understanding reset decisions in general.

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The official Xilinx position is to use sync reset. It's explained in this whitepaper, also mentioned in the above post. All Xilinx IP cores that come with the source code, such as memory controller, use sync reset.

My team experimented with different designs, and found that the advantage of using sync reset in term of logic utilization improvement is negligible.

The biggest advantage of using async reset is faster build runtime, which is substantial for large designs. The reason is that async reset paths are not covered by the synchronous timing constraints (you can cover them by adding separate constraints, if you want).