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How are FPGAs "Updated"

开发者 https://www.devze.com 2023-01-30 01:46 出处:网络
I seem to be under the impression that FPGAs can be updated while the chip is running; and I need to know开发者_StackOverflow if that is correct or not.

I seem to be under the impression that FPGAs can be updated while the chip is running; and I need to know开发者_StackOverflow if that is correct or not.

It seems to be from what I've read that you can change the FPGA netlist on demand the same way you can change the program that's running on a processor. Yes I know that an FPGA is not a processor.

Is my assumption correct, and if not then how come?


Most of the time, you load the configuration for the entire FPGA in one go, and all logic stops running during the reconfiguration process.

It sounds like you want to reload a subset of the FPGA, while the remainder continues running. You would need a device with special support for partial reconfiguration. There's more information on Wikipedia.


==> EDIT: I stand corrected: EETimes article on partial reconfiguration

You will generally need to reset the FPGA so that it can be reprogrammed.

At a system level reconfiguration is possible. You can have a software application running on a PC or embedded system that reprograms the FPGA as needed. Depending on the application or software license, you can program different FPGA designs easily. You cannot, however, significantly alter the design structure, such I/Os, logic cells, DSP configs, memory blocks, etc.


FPGAs have a bunch of logic cells that need to be initialized by a stream of configuration bits. This stream of bits usually comes from a flash chip located off the device, although some devices have the flash memory on-board.

Partial Reconfiguration means the ability to configure just some of the logic cells while the rest are in use. This is specific to particular models.

Total reconfiguration is possible even if your device doesn't support it - you would need to reprogram the flash chip and then issue a Reset or reload command when done.

Some devices have more than one configuration image in the configuration flash. The device will load the first image, and if it doesn't like it, it will load the second (or subsequent) images. This can be for redundancy, or difference feature sets.

Some of the SOC FPGAs (like Xilinx Zynq) use the microprocessor core to load the FPGA. In this case, the microprocessor core can change the FPGA as much as it wants while running.


Yes I know that an FPGA is not a processor.

An FPGA is is a type of processor, but it is not a type of CPU.

Most FPGAs only have volatile storage so you have to update them whilst they're on. This doesn't mean that you can change their operation any time you want. That's dynamic reconfiguration and only supported by a subset of FPGAs.

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