Preserving the widths of ports

I am trying to re-use netlists in other designs without the success.

I have a component which is translated to the netlist:

  entity c is
     port (...  sel : in std_logic_vector(31 downto 0); ... );

In the design I am using just sel(4 downto 0). The synthesis tools notices this behaviour and gives a warning:

'WARNING:Xst:647 - Input sel<31:5> is never used ..

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I am generating netlist with properties:

• keep hierarchy = true
• add I/O buffers = off

Whenever I want to instantiate this netlist as an black-box module in other circuit I got an error:

ERROR:NgdBuild:76 - cannot be merged into block because one or more pins on the block, including pin "sel<31>", were not found in the file.

How can I preserve the size of sel? I should mention that the sel needs to be 32bits width since it's connected to the bus.

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You could try driving the unused input ports to zero.

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Can you use the component directly instead of as a pre-synthesised black-box?

You may get things to work by putting a KEEP attribute (see your synth tools manual) on the port. I've only ever tried this on signals, but it may work.

This sort of task is often described as "pushing on the rope" of the synthesiser, as it's such a pain to get it to not be as celever as it wants to be (and then in the next release of tools you need a different attribute :)