Verilog to GDSII compiler (open-source)

May be this question a bit not for StackOverflow, but both compilers and Verilog (which can be considere开发者_StackOverflowd as programming language) are related to this project.

Where can I find a open-source (or downloadable and free-to-noncommercial-use) compiler from Verilog language to the GDSII format or to Netlist? There are a lot of Verilog simulators (which compile it to native machine code or to the C), a lot of Verilog-to-FPGA compilers, but I want compiler, able to generate geometric structures of transisors from Verilog.

Netlist is http://en.wikipedia.org/wiki/Netlist - interconnect of IC elements, such as transistor, resistor or even cells (?). It can be converted to GDSII, but if compiler works on "Verilog->Netlist", I also need a free convertor "Netlist->GDS2".

GDSII http://en.wikipedia.org/wiki/GDSII - is a format of VLSI integrated circuits (IC), which is acceptable by founrdies for IC fabrication. It is nearly impossible to a single human to get his GDSII fabricated in Silicon, but I think, it can be intresting to try of compiling small examples.

This compiler can use "full-custom" (it will draw all transistors itself), or "cell-based" designs (verilog is compiled into a geometric set of some library cells).

Of course, the compiler required can be a university project, which can't compile a big verilog project.

Thanks.

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Usually the steps are:

Verilog -> [Compiler] -> Gate-level netlist -> [Place & Route tool] -> GDSII

You'd need an open-source cell library too. Do a quick interweb search for that, and a place & route tool may show up.

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This may be the last open source computing stack to be conquer, We already have GNU/Linux, GCC, and perhaps some open source CPU's. But not a complete chip design flow. What you refer is what is known as Place and Route (P&R) in the Electronic Design Industry (EDA) jargon. As far as I know there is not a competitive VLSI flow in the open source community, the investment needed for the development of a complete place and route solution is very big in order of millions of dollars, example of this commercial tools are: Design Compiler, Encounter from Cadence, IC compiler from Synopsis among others. Some of the algorithms for P&R have origin in academia, you may find some code here and there, but not a complete solution.

You can find SPICE, a circuit simulator that foundries and CAD companies use to generate their cell libraries http://en.wikipedia.org/wiki/SPICE

These are some links to academic and open source standard cell libraries, http://www.vlsitechnology.org/ http://www.vtvt.ece.vt.edu/vlsidesign/cell.php But I'm not sure if they can be used for real production. But certainly is on of the first ingredients in the EDA tool flow.

Prof. Andrew Kahng from UCSD, is a researcher in VLSI at UCSD, he keeps a list of useful list of software for VLSI, here: http://vlsicad.ucsd.edu/Resources/SoftwareLinks/index.html but some of the EDA links are broken. This list from Berkeley may be helpful also: http://embedded.eecs.berkeley.edu/pubs/downloads/

If you or someone may find some P&R open source let me know. Hope this helps.

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Check out Fedora's FEL project: http://spins.fedoraproject.org/fel/#portfolio

Actual tools for cell design compilig are http://www-asim.lip6.fr/recherche/alliance/doc/design-flow/tools.html#boog (for VHDL only)