Reading OUT ports for debugging

I have a FIFO which has an interface that looks something like this:

entity fifo is
    port (
    CLK               : IN  std_logic := '0';
    DIN               : IN  std_logic_vector(31 DOWNTO 0);
    ALMOST_EMPTY      : OUT std_logic;
    ALMOST_FULL       : OUT std_logic;
    DOUT              : OUT std_logic_vector(31 DOWNTO 0);
    ...
    WR_ACK            : OUT std_logic
);
end fifo;

This interface is given and I can't change is. The thing is now, for debugging purposes, I wanna see what is written and read to/from the FIFO. In other words, ideally I wo开发者_如何学Gould like to assign two debug the in and out values of the FIFO, ie.

  DBG_FIFO_IN  <= DIN;
  DBG_FIFO_OUT <= DOUT;

For obvious reasons, the second assignment gives me the following error message:

[exec] ERROR:HDLParsers:1401 - Object DOUT of mode OUT can not be read.

So I am wondering if there is any way how I can assing the DOUT value to my debug symbol. The interface is given, so I cant make DOUT an inout signal.

Many thanks for helpful comments!

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You have to assign the fifo output to a local signal you can read, then assign that signal to the output (or assign them both in parallel):

DBG_FIFO_OUT <= (your logic here);
DOUT         <= DBG_FIFO_OUT;

or

DBG_FIFO_OUT <= (your logic here);
DOUT         <= (your logic here);

---

Use BUFFER instead of out. Then you can read without the intermediate signal used in Charles' solution.

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You have good answers already for older tools - but if you use some tool which supports VHDL-2008, you are allowed to read output ports directly. You may need to enable this with a command line option.

If your tools don't support it, whinge at the supplier until they do!