How do I implement a synthesizable DPLL in Verilog?

I开发者_Go百科s there any straight forward way to implement an all digital phase lock in synthesizable Verilog? Everything (including the VCO) should be synthesized. The signals I'm looking to lock to are ~0.1-1% of the system clock frequency. I am using one that I've reconstructed from 1980's IEEE papers, but it doesn't behave as well as advertised.

For simplicity, the lock can work on a binary pulse signal.

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In FPGA designs I normally use the built in DCMs, or PLLs.

The Cyclone 2 has up to 4 PLLs built in.

Have a look at PLLs in Cyclone 2.