VHDL Case/When: multiple cases, single clause

Inside a process I have something like this:

CASE res IS
  WHEN "00" => Y <= A;
  WHEN "01" => Y <= A;
  WHEN "10" => Y <= B;
  WHEN "11" => Y <= C;
  WHEN OTHERS => Y <= 'X';
END CASE;

Note that case "00" and "01" get the same value. Is there a correct syntax for something like

WHEN "00", "01" => ?

Extra note: There'开发者_运维知识库s far more to this than Y being changed, I just used that for simplicity. So the case/when is necessary.

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You can separate multiple choices with the "pipe" or bar symbol. The proper syntax for your example is:

CASE res IS
  WHEN "00" | "01" => Y <= A;
  WHEN "10" => Y <= B;
  WHEN "11" => Y <= C;
  WHEN OTHERS => Y <= 'X';
END CASE;

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You can also give a range of choices for a case:

USE IEEE.STD_LOGIC_ARITH.ALL;

CASE CONV_INTEGER(res) IS
  WHEN 0 to 1 => Y <= A;
  WHEN 2 => Y <= B;
  WHEN 3 => Y <= C;
  WHEN OTHERS => Y <= 'X';
END CASE;