How does a TABLE work in AHDL?

I have an implementation of a Control Unit (UC) in A开发者_StackOverflowHDL, and I'm supposed to simulate it and see if it works as defined in the correspondent ASM diagram. I used MAX+plus II to simulate it, and it doesn't work as I expected, but I can't really say what's wrong because I am not familiar with AHDL, let alone the TABLE part.

Here is my Control Unit:

SUBDESIGN EXP1_UC
(
CLKUC: INPUT;
RES: INPUT;
N1,N2,M1,M2: INPUT;

CLR1, CLR2, CLR3, EN1, EN2, EN3, SEL: OUTPUT;
)
VARIABLE
UC: MACHINE OF BITS (CLR1, CLR2, CLR3, EN1, EN2, EN3, SEL)
WITH STATES
(
s0 = B"1110000",
s1= B"0001000",
s2= B"0000100",
s3= B"0000000",
s4= B"0000010",
s5= B"0000001",
s6= B"0000011"
);
BEGIN
UC.CLK = CLKUC;
UC.RESET = RES;
TABLE
UC, N1,N2,M1,M2 => UC;
s0, 0, 0, X, X => s0;
s0, 1, X, X, X => s1;
s0, X, 1, X, X => s2;
s1, X, X, X, X => s3;
s2, X, X, X, X => s3;
s3, 0, 0, 0, 0 => s3;
s3, 1, X, X, X => s1;
s3, X, 1, X, X => s2;
s3, X, X, 1, X => s4;
s3, X, X, X, 1 => s5;
s4, X, X, X, X => s3;
s5, X, X, X, X => s6;
s6, X, X, X, X => s3;
END TABLE;
END;

There are 2 situations in the simulation which I don't understand:

1) When the current state is S3 and the inputs are M1 = 1 and M2 = 1, the next state is S6. I don't get that, because the way I see it, there is no way to go to S6 without passing through S5 first.

2) When the current state is S0 and the inputs are N1 = 1 and N2 = 1, the next state is defined in the simulation as "12". Well, there is no such state...

Can anyone help me? Thanks.

UPDATE:

1) I have to use ADHL and MAX+plus II even though it's hardly the best combination of tools, because this is a paperwork for college, and I didn't write the code (like I said, I am just supposed to simulate it, I can't change it).

---

First: do you really have to use AHDL? - it hasn't been a properly supported part of Altera-land for years. And MAX Plus II is a very old bit of software - get a hold of Quartus and learn VHDL (or Verilog if you must ;) would be my suggestion. Sorry if that sounds harsh!

But what your problem really sounds like is a traditional logic problem... are the inputs to your state machine properly synchronised? If not, you can get all sorts of weird effects as they change close to a clock edge and then the signals get to part of the state machine on one side of the clock and to other parts on the "other side" of the clock (ie not seen until next cycle). This will confuse things dreadfully! Also, make sure your reset signal is also synchronised to the clk signal.

Quick hack - stick two flip flops in a chain on each of the inputs. Then read up on synchronising asynchronous inputs...