NAND flash programming: granularity of writes?

is someone in the kow about write accesses on nowadays large NAND flash chips? What is the minimal granularity for writes? I have a microcontroller flash here which requires at least 1 and at most 4 words (16-bit words that is) to be fed to the write statemachine at once. I think that the large (> 1 Gbit) flashes behave differently here for write per开发者_如何学运维formance reasons.

slarti

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So to be clear, to write a 1 bit you have to clear a whole block of memory, to write a 0 bit you only have to write one memory location. Are you talking about a one time write (changing some of the bits from a 1 to a 0 essentially) or are you talking about erasing chunks and re-writing the chunk so that you can make some of the bits go from a 0 to a 1?

The easiest way to know is to just get the data sheet for the part in question or for a handful of them from different vendors. The most recent one I used, which was spi based, had something like a 0x10000 (65536) byte sized erase block. The older parallel ones I call them, the ones with a traditional address bus and data bus, had something like 256 byte or 512 byte pages, but these were not the newer technologies (nand).

EDIT

Looking at a randomly selected samsung document the megabyte sized memories had 256 and 512 byte page sizes, but the 1 and 2 gigabyte page sizes were not documented (it was family kind of datasheet and not a specific parts datasheet). The block sizes are in the 4K to 16K range for the MB sized memories.

This is cut from a web page, I googled nand flash page size:

"The other major change to the 25nm NAND is an increase in the page size. At 50nm and 34nm, IMFT’s page size was 4KB. At 25nm on the 8GB device the page size is now 8KB. Block size has also gone up from 128 pages to 256 pages."

Wikipedia has some interesting information as well for nand flash:

"While reading and programming is performed on a page basis, erasure can only be performed on a block basis. Another limitation of NAND flash is data in a block can only be written sequentially."

So that sounds pretty bad, you are looking at writes of 1s requiring a 2MByte erase. I use these things for booting embedded processors so I typically erase once and write once every blue moon or so and ideally a single erase and single pass of writing and done for the life of the product. For use as a disk like media, this is painful.

Also note nand and/or the smaller densities are exhibiting read-disturb issues where simply reading a location too often can erase near-by locations. Which may not be a problem for disk like media, but if you wanted to run (execute) an embedded processor out of nand flash, well you cant, you boot and with using minimal loops copy a small program to ram, branch to ram, have that small program/function have a loop that copies the rest of the program to ram and you run out of ram.

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It is completely dependent on the device, but is usually a power of 2.