Redundant loop inside a process (VHDL)?

I'm taking a university course to learn digital design using VHDL, and was doing some reading in the book the other day where I came across the following piece of code:

architecture abstract of computer_system is
    ...

    cpu : process is
        variable instr_reg : word;
     开发者_JAVA技巧   variable PC : natural;
        ...
    begin
        loop
            address <= PC;
            mem_read <= '1';
            wait until mem_ready;
            ...
        end loop;
    end process cpu;
end architecture abstract;

Now, as I've understood it, once a process reaches its last statement, it will go back and execute the first statement (provided that the last statement wasn't a wait, of course). And the purpose of loop ... end loop; is to repeat the intermediate code indefinitely. So doesn't that make the loop redundant in this case? Does it add any extra behaviour that isn't already exhibited by the process?

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You're spot on as far as I can see, no need to have a loop in there.