I am creating a Makefile which I want it to be a single file for different architectures, OSes, libraries, etc. To do this I have a build specific XML file which defines the different configuration options for each architecture. The config file is read by Perl (it could be any language) and the Perl output returns something like:
var1 := var1_value
var2 := var2_value
var3 := var3_value
What I am trying to do is define this variables in my Makefile. From the makefile I am calling my readconfig script and it is giving the correct output, but I have not been able to get this variables as part of my Makefile. I have tried the use of eval
and value
, but none of them have worked (although it could be an issue of me not knowing how to use them. In overall what I am trying to do is something like:
read_c开发者_如何学编程onfig:
$(eval (perl '-require "readConfig.pl"'))
@echo $(var1)
It could be assumed I am using only GNU Make behavior. Things I could not change:
- Config file is on XML
- Using Perl as a XML parser
I think the directive you are looking for is 'include':
include config.mk
...rest of makefile...
Your script generates the config.mk
file; the makefile reads it. If you need to have the makefile run the generator, it gets more intricate:
MAKEFILE_INCLUDE = dummy.mk
include ${MAKEFILE_INCLUDE}
all: normal dependencies for target
config: config.mk
perl make-config.pl > config.mk
${MAKE} MAKEFILE_INCLUDE=config.mk
You'd run make config
first (with only an empty or almost empty dummy.mk
file). It would then run make. It is simpler if you don't try this; other targets than all
become tricky, etc. There are ways, but they are increasingly contorted.
There's no need to have config.mk as an explicit target; if you include it, Make will make it (if necessary):
-include config.mk
all: real_targets
config.mk: xml_file
perl make-config.pl > $@
A version which make the config to be part of the default `all' target.
-include config.mk
all: config.mk and other targets
config.mk:
perl make-config.pl >config.mk
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