How do I get rid of sensitivity list warning when synthesizing Verilog code?

I am getting the warning that:

One or more signals are missing in the sensitivity list of always block.

always@(Address)begin
  Re开发者_高级运维adData = instructMem[Address];
end

How do I get rid of this warning?

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Verilog does not require signal names in the sensitivity list. Use the @* syntax to signify that the always block should be triggered whenever any of its input signals change:

always @* begin 
    ReadData = instructMem[Address]; 
end 

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Add InstructMem to the sensitivity list.

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Declare ReadData as a wire instead of a reg and then replace your always block with an assign.

assign ReadData = instructMem[Address];

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I am not sure what the declaration of instructMem looks like. Anyway, ReadData = instructMem[address] is going to result in a multiplexer with address being treated as selection logic and instructMem as data lines of the multiplexer using a typical synthesis tool. You would need to put in instructMem in the sensitivity list since whenever this changes so should ReadData.

I tried Icarus, and you anyway cannot do something like always @(instructMem or address) where instructMem has a declaration like reg [7:0] instructMem [255:0] --> implying memory.

Note: do not try to synthesize Verilog memories this way, typically you are supposed to instantiate memory IPs and connect to their ports. Vendors provide memory models for such purposes.