**** Build of configuration Debug for project myso ****
make all
filename.d:1: *** multiple target patterns. Stop.
The makefile looks like:
# All Target
all: libmyso.so
# Tool invocations
libmyso.so: $(OBJS) $(USER_OBJS)
@echo 'Building target: $@'
@echo 'Invoking: GCC C++ Linker'
g++ -L"E:\cygwin\lib" -shared -o"libmyso.so"
$(OBJS) $(USER_OBJS) $(LIBS)
@echo 'Finished building target: $@'
@echo ' '
# Other 开发者_开发知识库Targets
clean:
-$(RM) $(OBJS)$(C++_DEPS)$(C_DEPS)$(CC_DEPS)$(LIBRARIES)$(CPP_DEPS)$(CXX_DEPS)$(C_UPPER_DEPS) libmyso.so
-@echo ' '
.PHONY: all clean dependents .SECONDARY: -include ../makefile.targets
The makefile that you posted (I hope I got the formatting correct) refers to another makefile, and the contents of that other makefile are probably important. However, it appears that your problem is that filename.d
is found in a path with spaces, and that path is what appears in either $(OBJS)
or $(USER_OBJS)
(probably defined in ../makefile.targets
).
EDIT It looks like this is a problem that has been fixed in some version of Make, but not yours (see "Compiling on Cygwin").
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