my makefile's target-specific variable doesn't affect recursively expanded variables [duplicate]

This question already has answers here: Closed 11 years ago.

Possible Duplicate:

Target-specific Variables as Prerequisites in a Makefile

In my makefile (rather simplified below) I have 开发者_高级运维a target-specific variable that needs to influence a recursively expanded variable, but it's not doing so - leaving me sitting here scratching my head:

NAME            = MyProg
OBJECTS         = $(OD)/main.o
RD              = Release
OD              = Foo

all: OD = $(RD)
all: $(OD) $(OD)/$(NAME).elf

$(OD):
    mkdir $(OD)

$(OD)/$(NAME).elf: $(OBJECTS)
    $(CC) $(LDFLAGS) -o "$@" $^

$(OD)/%.o: %.c
    $(CC) $(CFLAGS) $(INCLUDES) -Wa,-a="$(OD)/$*.lst" -o "$@" "$<"

The command that actually gets executed is as follows:

gcc -O2 -Wall -Wstrict-prototypes -c -Wa,-a="Release/main.lst" -o "Foo/main.o" "main.c"

$(OD) is correctly evaluated in the ".lst" expression, but incorrectly by $(OBJECTS). It must be that $(OBJECTS) is evaluating $(OD) outside my rule... so is it possible to correct this behavior? Where am I making the mistake?

---

The Make manual says this about target-specific variables

"these values are only available within the context of a target's command script (and in other target-specific assignments). " 1

and I guess this is what you are seeing, the target-specific variable is not expanded in targets themselves.

What is it you're trying to accomplish?