What is a 'make target'?_问答_开发者_运维开发者技术经验分享

Why do I need to make a make target before being able to开发者_运维问答 build my source code?

More specifically, what is make target exactly?

Makefiles look like this:

all: mybinary

mybinary: files.o it.o depends.o on.o
[tab]$(CC) $(CFLAGS) files.o it.o depends.o on.o -o mybinary

files.o: files.c files.h
[tab]$(CC) -c $(CPPFLAGS) $(CFLAGS) $< -o $@

...

This means, when you type make all (the shorthand is just to type make), it will make sure that the mybinary target or file is up to date. To do that, it needs to make sure that mybinary is newer than all of files.o it.o depends.o and on.o. If not, then it uses the shell commands specified on the next line to build mybinary. But before doing that, it first makes sure that files.o and so on are up to date. This means they have to be newer than files.c and files.h. If not, then it uses the shell commands specified on the next line to build files.o. Once all the *.o files are up to date, it can build mybinary. Once mybinary is built, the all target is satisfied.

Targets are usually just files. The format of a block is:

target: list of dependency files
[tab]shell commands to build target if it's older than any of its dependencies
[tab]more shell commands
[tab]still more

Targets can also be specified using wildcards, for instance %.c means what in the shell you'd call *.c.

Some targets are "phony" targets meaning they don't correspond to any real file. The "all" target is of this sort. So too is the "clean" target (make clean). And so on. You don't really need or want to build a file called "all" or "clean". There are various ways to specify that a target is phony.

The first target to appear in the Makefile is the one that will be invoked if you simply type make. One convention is to name this target "all". So then make will be the same as make all.

A 'make target' is basically a file that you want rebuilt.

Make can't divine what you want built, so you have to tell it, implicitly or explicitly, what it should build. Often, the first target in the file is a name such as 'all' and if you run 'make' without any explicit target, it will build the first target listed in the makefile. However, some makefiles do not specify any target; then you must specify one on the command line. Or, if you don't want the default target built, then you must specify the target that you do want built.

A target can also be 'phony', in the terms of GNU make. That is, it is a name that does not exist, and the rules do not create it, but it (the phony target) depends on a number of other files that do have rules associated with them. Indeed, the 'all' target is usually a phony target - there isn't a file called 'all' in most directories.

A makefile will usually include code to make your program, install your program, clean up afterward, and other things.

so the word target could be various keywords, such as all, install, clean, etc.

It's a way of saying make something. make all implies do everything

make is a common development tool, which checks file dates between source code files and the object code produced from them, and compiles the one where the source is newer. It does this by use a file, called a makefile, which list the files that need to be compared.

The standard syntax is make /f makefile myprog.exe

That says to build myprog.exe using the file list in makefile. The makefile defaults to makefile.mak so if you use that name, you don't have to specify it on the command line.

myprog.exe here is called the target. One trick is that you could put in the makefile a list of build instructions for a non-existant file. If you then say to build that target, it will run those command. Often, you'll see something like make clean, which has temporary file deleted.

In real life, when you want to achieve something, you usually call that something a goal, or target. To reach that target, usually you need to achieve some pre-requisites.

In computer domain, target has a similar meaning. It is not necessarily limited to build software. But it is often seen when building software.

A piece of software is usually composed of a lot of components. And these components usually have inter-dependencies. Let's say to completely build a software is your ultimate target. And to achieve that, you need to build components with respect to their dependencies. You can image organizing the components into a hierarchy, like a tree. And each node is a intermediate target with the root as the ultimate target, usually it is named all. You can invoke make for any of the target nodes, intermediate or root. And then all its sub-targets need to be completed to make the target node complete.

For each target, you need to specify the actions to take to complete that target. These actions are called commands or rules.

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