schematic for verilog code that adds three inputs

What does the schematic looks like for the following verilog code?

module mystery2(s, c, x, y, z);
  input x, y, z;
  output s, c;
  assign {c, s} = x + y + z;
endmodule

I know that {c, s} means that they are concatenated, what开发者_StackOverflow中文版 does this looks like in schematics? And x + y + z is just an add between the three inputs, right? And we have one wire coming out of it?

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You can think of x + y + z as the sum of 3 1-bit wires, but the sum requires 2 bits. Thus, I would consider {c,s} as 2 1-bit wires "coming out".

The answer to your main question depends on how the circuit is implemented. There are many possible schematic representations for your code because you have described a digital logic function at a high level of abstraction.

Run that code through your synthesis tool and see what kind of a gate-level netlist is produced. Then look at it in a schematic viewer. Let the tools do the work for you.