how can i know if my code is Synthesizable? [Verilog]

In designing a circuit in verilog using top-down method, I can start from the behavior of a circuit followed by defining the details in every module to construct a structu开发者_如何转开发ral circuit that is synthesizable. But how can I know if my code is synthesizable? Are there any guidelines to follow to support synthesis in verilog?

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There is a 'standard', IEEE 1364.1 but as Martin pointed out each tool supports whatever it wants. I recommend the Xilinx XST User Guide if you need a free resource.

Also, structural verilog typically means you are creating description close to a netlist and the constructs you would use in this case are a small subset of those that are synthesizable.

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Read the documentation that comes with whatever synthesis tool you are going to be using. This will show you what you can do - sometimes there are very specific ways you have to write code to get the intended results.

Ultimately though, there's nothing to beat experience - run your synthesiser over your code (or small parts of it) at regular intervals and see what the tool produces.