I am given the following diagram with the text. The author refers the AND
gate which becomes the control signal PCSrc
. But I am unable to make this relation from the diagram.
Here is the text,
ALU performs comparison of registers in the branch instruction and produces a HIGH logic on its ZERO output. This ZERO output ANDed with control signal Branch is used to indicate a taken branch. The output of this AND gate is the control signal PCSrc which controls a multiplexer that chooses between address of next sequential address (when the branch is not taken) and BTA (开发者_JAVA百科when the branch is taken). BTA is calculated by a dedicated adder.
I am not sure exactly which part you don't make relation from. Here goes an explanation where I circled in the diagram the different blocks used to compute the next PC address to be used.
Block 1 is just an adder which adds 4 to the current PC address (therefore giving you nPC, the next PC address).
The ALU in block 2 is used to do the branch comparison. Upon doing the comparison, it will reflect in the Zero flag whether the two compared values are equal. This output is used in block 3 (the AND gate) to compute the PCSrc flag. It will be 1 only when the Branch signal from the control block is 1 and also the Zero flag of block 2 is 1, thus selecting the result from ALU adder in multiplexor block 4. Otherwise, the multiplexer will output nPC computed by block 1 described before.
Then, multiplexor block 5 chooses between the unconditional jump address (selected only when in an jump instruction) or the output of multiplexer 4 described above, and the selected address is stored on PC register.
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