Programmable Logic Devices

I have a confusion in understanding the structure of PAL device.

My first question is that if we buy a PAL device , then how can we know that how many min terms are added by each OR gate in the OR array? In other words I am asking, is ther开发者_开发百科e any standard by which we can know the number inputs each OR gate has in the OR array?

The next thing is that we have an AND array in the PAL device which is programmable. Now suppose we have 4 inputs , then each AND gate in the AND array must need 8 inputs. It is up to us how many variables we apply on it, but there is a possiblity that we can apply all the variables on the AND gate therefore it should have 8 inputs. Please tell me am i right or not. If not then please explain.

---

I think there is no universal standard for either of your questions. The data-sheet for each device specifies those parameters. You should look up the data-sheets and decide what suits your needs.

Specifically on your second question, an ideal PAL should be as you say (like this simplified circuit). But usually you don't want to apply all the variables (and their negations) to the AND gates, so each AND gate can have less inputs (of course using the grid you can choose any of the variables to apply, just not all of them together).