USRP2 FPGA debugging

I have added some functionality in the FPGA code( Verilog) in USRP2. I would like to debug the code. Can you please suggest开发者_JS百科, how to debug the FPGA code .

I donot want to write the testbench for the module. Is it possible that I could write to a buffer in the FPGA code and read this buffer from the firmware and read it from the serial console of the USRP2.

Any hints/ direction would be highly helpful.

Thanks Kiran

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You can debug your code in 2 different ways, one is using the debug port available on the unit the second one is to use the JTAG port and use the ChipScope to debug your code.

This is from the GR site: http://gnuradio.org/redmine/projects/gnuradio/wiki/USRP2UserFAQ#Is-there-a-JTAG-port

Is there a JTAG port?

Yes, there is a standard JTAG header on the board connected to the FPGA and a CPLD, but you may not need it. Since the FPGA is programmed from the SD Card by the bootstrapping CPLD, the main utility of the JTAG port is to reprogram the CPLD. You may be able to use the JTAG port with ChipScope.

And this is the answer Nick Foster replied to on the GR mailing list:

There's a debug port (MICTOR connector) on the USRP2 (J301) which you can route signals to for debugging. It's connected to the 32-bit wire "debug" in u2_core.v. Just connect signals you're interested in to debug and use a logic analyzer.

BR, Farhad