using variable before it is defined

   process is
         variable a_var, b_var : std_logic ?
   begin
         wait until ( rising_edge ( clk ) );

             a_var := x开发者_开发问答 or y ;
             b_var := a_var nor z ;
             res   <= b_var xor y ;

   end process:

In this case, IS the variable b_var used before it has been defined ? If yes, can one explain why .

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No, you've quite clearly defined it on the variable line. You've also set the value of b_var before you use it in the process, which means that no flip-flop will be inferred for it.

Your code is the equivalent of

FOO: process(clk)
begin
    if rising_edge(clk) then
        res <= ((x or y) nor z) xor y;
    end if;
end process FOO;

(I've overlooked a couple of syntax errors in your code, assuming them to be just typos.)