VCD Dump of only a sub part of the design via modelsim

I have a big design that includes a test-bench, some testing circuit and the circuit under test itself. I use modelsim to simulate the design and I want to have a dump of the simulation. I was suggested to generate the dump using the command:

vcd file myvcd1.vcd
vcd add -r /sim_minimips/*

it seams to work but what i would like is to generate the dump only for the circuit under test.

i tried to use the same command in specifying just the name of the file i would like to be taken in consideration:

vcd file myvcd2.vcd
vcd add -r /minimips/*

but the following error was generated:

Error vsim 3561 No object matching minimips

I do not understand the error and i am not sure even if this is the correct procedure to isolate a subpart.

does anyone knows how to do or knows where could i get a decent simply tutorial about this Value Change Dump?

I attach my test bench entity:

library IEEE;
use IEEE.std_logic_1164.all;

library std;
use std.textio.all;

library work;
use work.pack_mips.all;

entity sim_minimips is
end;

architecture bench of sim_minimips is

  component minimips is
  port (
      clock    : in std_logic;
      reset    : in std_logic;

      ram_req  : out std_logic;
      ram_adr  : out bus32;
      ram_r_w  : out std_logic;
      ram_data : inout bus32;
      ram_ack  : in std_logic;

      it_mat   : in std_logic
  );
  end component;


  component ram is
    generic (mem_size : natural := 256;
             latency : time := 10 ns);
    port(
        req        : in std_logic;
        adr        : in bus32;
        data_inout : inout bus32;
        r_w        : in std_logic;
        ready      : out std_logic
  );
  end component;

  component rom is
  generic (mem_size : natural := 256;
           start : natural := 0;
           latency : time := 10 ns);
  port(
          adr : in bus32;
          donnee : out bus32;
          ack : out std_logic;
          load : in std_logic;
          fname : in string
  );
  end component;

  signal clock : std_logic := '0';
  signal reset : std_logic;

  signal it_mat : std_logic := '0';

  -- Connexion with the code memory
  signal load : std_logic;
  signal fichier : string(1 to 7);

  -- Connexion with the Ram
  signal ram_req : std_logic;
  signal ram_adr : bus32;
  signal ram_r_w : std_logic;
  signal ram_data : bus32;
  signal ram_rdy : std_logic;

begin

    U_minimips : minimips port map (
        clock => clock,
        reset => reset,
        ram_req => ram_req,
        ram_adr => ram_adr,
        ram_r_w => ram_r_w,
        ram_data => ram_data,
        ram_ack => ram_rdy,
        it_mat => it_mat
    );

    U_ram : ram port map (
        req => ram_req,
        adr => ram_adr,
        data_inout => ram_data,
        r_w => ram_r_w,
        ready => ram_rdy
    );

    U_rom : rom port map (
        adr => ram_adr,
        donnee => ram_data,
        ack => ram_rdy,
        load => load,
        fname => fichier
    );

    clock <= not clock after 20 ns;
    reset <= '0', '1' after 5 ns, '0' after 70 ns;
    ram_data <= (others => 'L');

    process
        variable command : line;
        variable nomfichier : string(1 to 3);
    begin
        write (output, "Enter the filename : ");
        readline(input, command);
        read(command, nomfichier);

        fichier <= nomfichier & ".bin";

        load <= '1';
        wait;
    end process;

    -- Memory Mapping
    -- 0000 - 00FF      ROM

    process (ram_adr, ram_r_w, ram_data)
    beg开发者_运维百科in -- Emulation of an I/O controller
        ram_data <= (others => 'Z');

        case ram_adr is
            when X"00001000" => -- program an interrupt after 1000ns
                                it_mat <= '1' after 1000 ns;
                                ram_rdy <= '1' after 5 ns;
            when X"00001001" => -- clear interrupt line on cpu
                                it_mat <= '0';
                                ram_data <= X"FFFFFFFF";
                                ram_rdy <= '1' after 5 ns;
            when others      => ram_rdy <= 'L';
        end case;
    end process;

end bench;

Cheers, Ste

---

The last parameter for vcd add is the design hierarchy path (using instance names) of the signal(s) you want to add (the * means all signals, though with the -r signal it also expands to all levels of the design below the hierarchy you've specified).

Thus, if your minimips is instantiated within sim_minimips using the instance name i_minimips, the correct way to add all signals in (that particular) minimips and any blocks it might instantiate is

vcd add -r /sim_minimips/i_minimips/*

If you want to restrict the items to add to the VCD a bit further, you could add one or more of the parameters -in, -inout, -out, -internal or -ports, which select only items of these types. Or leave out the -r to not descend into the hierarchy -- a common usage is vcd add -ports /sim_minimips/minimips/* which will add only the ports of the design top level, suitable for generating stimulus for many types of test benches.

It should be noted that vcd add works "just" like wave add, i.e. the object specification is in exactly the same format. Thus, often the simplest way to add items to a VCD is to add them to a wave in the Modelsim UI, copy-pasting the command from the transcript, and simply changing the wave add to a vcd add.

Also, file names are of no consequence here, only the structure of the design itself. For example, if you have something like:

entity sim_minimips is
    port (
        -- ...
    );
end sim_minimips;

entity minimips is
    port (
        -- ...
    );
end minimips;

architecture tb of sim_minimips is
    component minimips
        port (
            -- ...
        );
    end component;
begin
    I_MINIMIPS: minimips
        port map (
            -- ...
        );
end architecture tb;

In this case, the path to your minimips instance is /sim_minimips/I_MINIMIPS/.

---

The answer to the question is already given in the previous post. Given below is an alternative method to generate the VCD file in Modelsim which will be accepted by Tetramax ATPG tool by Synopsys

# Simulate the design
vsim -novopt work.mips_tb

# Create the VCD file
vcd dumpports -file mips.vcd /mips_tb/tb/*

My testbench (for reference)

module mips_tb;
mips_core tb
        (
            clk,rst,cop_dout,
            din,  ins_i,iack_o,cop_addr_o,
            cop_data_o,cop_mem_ctl_o,  addr_o,
            dout,  pc_o,  wr_en_o
        );
...