How to stream a small video in spartan 3e fpga?

By Using cosmiac tutorial 13 http://www.cosmiac.org/tutorial_13.html and ISE 10.1 the pdf file shows how to generate an image and you can download the project by clicking the first .zip file. At the end of the project it says...Now try to stream a small video in similar method. Note: Need to modify the Matlab file appropriately to obtain the pixel information and the reader.vhd to the used video specifications. Also need to get a video which uses only the 8 colors (which can be represented by Spartan-3E board) in order to get a clean output.

My questions are... If I have the matlab .coe files(video frames), do I use a single port ram(what type of ram in the core memory generator) to stream a small video? and how do I modify the reader below?

Lets say I start with 2 frames(2 images).I want show it back to back like a video or 1 on top of another(easier).

Things to remember..vhdl programming language, Xilinx ise any version(I can update), Xilinx Impact.

---------------------------------------------------------------------------------
-- File Name: reader.vhd
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity reader is
Port ( clk, reset : in  STD_LOGIC;
       row : in  STD_LOGIC_VECTOR (9 downto 0);
       col : in  STD_LOGIC_VECTOR (9 downto 0);
       addr : out  STD_LOGIC_VECTOR (15 downto 0);
       ennormal, enencryp : out std_logic;
          datain : in  STD_LOGIC_VECTOR (2 downto 0);
          dataout : out  STD_LOGIC_VECTOR (2 downto 0));
end reader;

architecture Behavioral of reader is

constant vtop : integer := 128;
constant vbottom : integer := 351;

constant htop1 : in开发者_运维问答teger := 64;
constant hbottom1 : integer := 287;
constant htop2 : integer := 352;
constant hbottom2 : integer := 575;

signal addr_normal : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal addr_encryp : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');

signal en_normal : std_logic := '0';
signal en_encryp : std_logic := '0';

begin

ens : process (clk, reset)
begin
    if reset = '1' then
            en_normal <= '0';
            en_encryp <= '0';       

    elsif clk'event and clk='1' then

            if (row >= vtop) and (row <= vbottom) then

                if (col >= htop1) and (col <= hbottom1) then
                        en_normal <= '1';
                        en_encryp <= '0';
                elsif (col >= htop2) and (col <= hbottom2) then
                        en_normal <= '0';
                        en_encryp <= '1';
                else
                        en_normal <= '0';
                        en_encryp <= '0';
                end if;

            else
                    en_normal <= '0';
                    en_encryp <= '0';
            end if;

    end if;

end process ens;

c_normal: process (clk, reset)
begin
        if reset = '1' then

            addr_normal <= (others => '0');

        elsif clk'event and clk='1' then

            if en_normal = '1' then

                if addr_normal = 50175 then
                    addr_normal <= (others => '0');
                else
                    addr_normal <= addr_normal + 1;
                end if;

            end if;
        end if;
end process c_normal;

c_encryp: process (clk, reset)
begin
        if reset = '1' then

            addr_encryp <= (others => '0');

        elsif clk'event and clk='1' then

            if en_encryp = '1' then

                if addr_encryp = 50175 then
                    addr_encryp <= (others => '0');
                else
                    addr_encryp <= addr_encryp + 1;
                end if;

            end if;
        end if;
end process c_encryp;

addr <= addr_normal when (en_normal = '1') else addr_encryp;

dataout <= datain;

ennormal <= en_normal;
enencryp <= en_encryp;

end Behavioral;

---

When most people talk about video, they mean a lot of data. Much more data than a low-end 15-years-old FPGA could possibly contain as a block RAM. Even with compression taken into account. Especialy with compression taken into account, because there is almost no way for this FPGA to decode any efficient video codec.

So unless you're trying to do something very retro or exotic (or both), i do not recommend storing video in BRAM. Look for the FPGA with a DRAM controller, and use external DDR1/2/3/whatever instead.

Back to your question, if you intend to store video in BRAM, you can set it up as single port ROM with default values, just add your coe file in the block ram generator GUI. The question is, how do you intend to output the video? Do you have some RGB/VGA monitor connected? Or an NTSC coder with analog TV? Or HDMI? You will need a controller to output your video, and in some cases it might not fit into your FPGA as well.