How to use "Chains of Implicit Rules" for Makefiles

GNU Make supports ``chains of implicit rules". What I want to achieve is to write in a single section of a Makefile to achieve this:

1. generate A into B with command, as: cmd1 A B
2. generate B into C with command, as: cmd2 B C
3. generate C into D with command, as: cmd3 C D

With A, B, C and D are four files with different extensions (denote .p, .q, .r and .t, for example). B and C are intermediate files which I do not need, while A is the source file and D is the output. The problem is that A is actually a very large set of files. So I want to use chain of implicit rules of Makefile to achieve this. But I don't know how to know the file names for intermediate files B and C, as in:

%.t : %.r : %.q : %.r
        cmd1 $< ?
 开发者_运维技巧       cmd2 ? ??
        cmd3 ?? $@

where ? and ?? are names for intermediate files. I haven't found very specific explanation on how to name these files. The GNU make manual page only provides variable representations such as $< and $@ which are not of immediate use for me. Thanks a lot.

---

You should split the rules into separate parts:

%.t: %.r.tmp
    cmd1 $< $@

%.r.tmp: %.q
    cmd2 $< $@

%.q: %.r
    cmd3 $< $@

When you make target.t, the intermediate target.r.tmp, target.q would generated for you, and they are removed at the end.

EDIT

If the intermediate files *.r.tmp, *.q are not used anywhere except for cmd2, cmd3, personally I don't feel like to create implicit rules.

Though "Chains of implicit rules" is a good pattern, it's not necessary in case of Makefile, IMO. Again this is just a personal feel.

%.t: %.r
    cmd1 $<       $*.r.tmp
    cmd2 $*.r.tmp $*.q
    cmd3 $*.q     $@
    rm -f $*.r.tmp $*.q