makefiles and their targets and dependencies

I have a question on my mind regarding makefiles.

$(OBJECTS) : OBJEC/%.o : %.c
        gcc -c $< -o $@

I am unable to understand this rule.

Usually, there is only one target and its dependencies in a makefile rule, but there are 2 colons in the above piece of code.

I am unable to figure out which is the target and which is the dependency. How does the 开发者_如何学Ccode work?

Can anyone clear it up for me?

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It's a static pattern rule. Have a look at this section of GNU make's manual.
Basically, it states that the pattern OBJEC/%.o : %.c only applies to the targets listed in $(OBJECTS).