Understanding CMOS performance and complexity for ASIC : 350nm to 45nm process

I am trying to build an ASIC chip with the help of the MOSIS project. (They make it cheaper by combining multiple small project into a single fab). I have a choice between 350nm to 45nm, and everything in between.

My project consists of a implementing in hardware, the sha256 algorithm. I have 1 pipeline of gates that is performing the algorithm. This single pipeline has about 50,000 to 75,000 gates.

Ideally I would like to fit multiple pipe开发者_开发知识库lines on a 350nm process. I am not sure if 350nm is small enough for this. Where can I find information about the number of gates that can be expected to be put on a 350nm process to 45nm process, of 0.063mm^2

Also, what is the performance of each process. Each step of my pipeline has delays of less than 100 pico seconds. Can I get a fast clock of 80MHz or more on 350nm?

Thank you.

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Try synthesizing your design for both 45nm and 350nm. I would guess that 45nm is going to give you more performance,less area and less delay.