what's wrong with my VHDL sine function gen?

library IEEE;
use IEEE.MATH_REAL.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;

entity SineGen is
    Port (clock             : in  std_logic;
          dac_ab_vpp        : in  integer range 0 to 4095;
          dac_cd_vpp        : in  integer range 0 to 4095;
          sine_dac_ab       : out std_logic_vector(11 downto 0);
          sine_dac_cd       : out std_logic_vector(11 downto 0));
end SineGen;

architecture Behavioral of SineGen is

subtype slv is std_logic_vector(11 downto 0);


begin

        process(clock)
            variable count       : integer range 0 to 255  := 0;
            variable temp_dac_ab : integer range 0 to 4095 := 0;
            variable temp_dac_cd : integer range 0 to 4095 := 0;

        begin   
            if rising_edge(clock) then

I tried everything and it comes down to that the next two lines makes the output always zero, and I don't understand why. It should've been an output with a sine function. (count is the 256 samples per period. n is the number of bits.) Are the following in valid format?

                -- A*sin (2PI/2^n * count)
                temp_dac_ab := dac_ab_vpp * integer(round(sin(real(count * integer(math_2_pi/real(256))))));
                temp_dac_cd := dac_cd_vpp * integer(round(sin(real(count * integer(math_2_pi/real(256))))));

                if count < 256 then 
                    count := count + 1;
                else
                    count := 0;
                end if;

                sine_dac_ab <= conv_std_logic_vector(temp_dac_ab, slv'length); 
                sine_dac_cd <= conv_std_logic_vector(temp_dac_cd, slv'length); 

            end if;


   开发者_运维技巧     end process;
end Behavioral;

---

In addition to what has been pointed out by @brianreavis, you don't want to convert the fraction math_2_pi/real(256) to an integer, since that will always be 0. So:

temp_dac_ab := integer(round(dac_ab_vpp * sin(real(count) * math_2_pi/real(256))));
temp_dac_cd := integer(round(dac_cd_vpp * sin(real(count) * math_2_pi/real(256))));

---

I'm realllyyy rusty with my VHDL, but I think you're wanting this:

temp_dac_ab := integer(round(dac_ab_vpp * sin(real(count * integer(math_2_pi/real(256))))));
temp_dac_cd := integer(round(dac_cd_vpp * sin(real(count * integer(math_2_pi/real(256))))));

(You don't want to round / cast the float coming from sin until after you multiply it with dac_ab_vpp / dac_cd_vpp)