Conditional OR in makefile

I'd like to enable a verbose compilation in my makefile, but I can't figure out how to make a conditional OR.

Let me explain: I want to be able to specify a verbose compilation either by setting V=1 or VERBOSE=1. I want to keep VERBOSE=1 available because we have some scripts that make use of it (and use other makefiles only aware of VERBOSE)

So the result must be that these two commands are the same:

make all VERBOSE=1 # pain to write
make all V=1

Now, my makefile looks like this today:

ifdef VERBOSE
[issue compilation commands with verbose mode]
endif

What I'd like to achieve is close to the preprocessor in C:

if defined(VERBOSE) || defined(开发者_运维问答V)
[issue compilation commands with verbose mode]
endif

Do you know how to do that?

---

I do like this:

ifneq "$(or $(LINUX_TARGET),$(OSX_TARGET))" ""

endif

Similar to the $(strip approach, but using the more intuitive $(or keyword

---

VERBOSE := $(or $(VERBOSE),$(V))

...then...

ifeq ($(VERBOSE),1)
#Conditional stuff
endif

---

I like Neil Butterworth's approach, but if you really want to do it in the style you describe, this will give you OR:

ifneq "$(strip $(VERBOSE) $(V))" ""
[be verbose]
endif

---

As far as I know, the conditional stuff in GNU make doesn't allow for ORs and ANDS. You could always do something like:

ifdef VERBOSE
DOVERBOSE = yes
endif
ifdef V
DOVERBOSE = yes
endif

ifeq( $DOVERBOSE, yes )
    main verbose stuff here
endif

but I don't see why you need to introduce the (hardly self documenting) define of V in the first place.

---

Ok, really late to the party, but I came across this, and wanted to add another solution for others who were looking how to add logic to makefiles: basically, do the logic in a shell, and get the output that way.

ifneq ( $(shell ( [ $(VERBOSE) ] || [ $(V) ] ) && echo y ),)

it seems more convoluted, but if you have an if statement with many ands and ors, this offers a lot of flexibility, and would be easier to read than nested $(and .. $(or ...)) statements.