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global constant in Verilog

开发者 https://www.devze.com 2023-03-06 05:18 出处:网络
I want to make a global constant that can be seen by all modules. I have tried different ways to declare a variable in the top module. However other modules don\'t recognize it.

I want to make a global constant that can be seen by all modules. I have tried different ways to declare a variable in the top module. However other modules don't recognize it.

In my top module I have the following:

`define MODELSIM 0

When I'm in Xilinx, I will set MODELSIM to 0. When I'm in Modelsim, I will set it to 1.

In other modules in other files, I will have the following:

  if(MODELSIM)

so that different things will happen depending on whether I'm in开发者_JAVA技巧 Modelsim or Xilinx.


There are a few things to be aware of. Getting the simple one out of the way first, references to preprocessor macros in verilog must be prefixed with a backtick, i.e.:

if (`MODELSIM)

The verilog standard specifies that tick-defines have global scope, meaning that if you define MODELSIM in the first file that is compiled, that definition will apply to all subsequent files. However, I believe Modelsim compiles each file in a separate compilation unit, so the safest thing to do is to create a mydesign.vh header with your macro definitions, and `include it in each verilog file. `define works at the level of the source text. There is no association between a `define and specific module, and no way to access a `define by scope.

A few stylistic notes:

  1. If you are trying to make a distinction between simulation and synthesis, it is standard to use the SYNTHESIS macro for this. Many synthesis tools will define it automatically. Be judicious about making things conditional on synthesis. Since it is intentionally causing your simulation to differ from your synthesized result, it's an easy way to shoot yourself in the foot.

  2. For simple flags, it may be better to use values of 1/undef rather than 1/0. Defining things to be zero can result in problems if you later write `ifdef MACRO.


For synthesizable code, there is no such thing as a global variable. You must route any such signals through your design.


Just prefix it with the name of the top-level module.

module top;
  integer myglobalvar;
endmodule

module any;
  initial $display(top.myglobalvar);
endmodule
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